Many of today's processors are implemented in a multi-core form including multiple independent cores and additional logic, often referred to as an “uncore,” which contains shared cache memory, controllers, input/output (I/O) circuitry, power control circuitry and so forth. In general, when a processor enters a low power mode of a given level, circuitry of one or more cores can be disabled to reduce power consumption when the cores are not needed to perform useful work. Nonetheless in these modes, such as so-called C-states of an Advanced Configuration and Power Interface (ACPI) Specification (e.g., Rev. 3.0b, published Oct. 10, 2006), the uncore remains fully powered.
As a result of this powered-on feature of the uncore, an undesired amount of power consumption of an overall processor socket can still occur in a low power mode. This is particularly so in certain processors such as server processors in multi-socket platforms, since these devices typically push the envelope in terms of the number of uncore units such as last level cache banks, cache controllers, off-chip links, memory controllers, and so forth. To accommodate this functionality, a significant amount of logic can be present in the uncore which in turn results in a significant amount of dynamic power consumption even when the socket is idle. This is a problem since both customers and regulatory bodies are demanding significant reductions in server idle power consumption.